1. Field of the Invention
The present invention relates to a substrate holding device for holding a substrate, such as a semiconductor wafer (made of Si, GaAs, InP, or the like), or a quartz substrate or a glass substrate having a plurality of island-like semiconductor areas formed thereon. The present invention also relates to a polishing method and a polishing apparatus employing the substrate holding device.
2. Description of the Related Art
The production of increasingly ultra-fine semiconductor devices and semiconductor devices having a larger number of layered wirings has resulted in an increasing demand for more precision in the flatness in a plane (i.e., planarization) of semiconductor wafers (made of Si, GaAs, InP, or the like) or quartz or glass semiconductors having a plurality of island-like semiconductor areas on their surfaces. In addition, with the advent of SOI (Silicon On Insulator) wafers and the necessity of three-dimensional integration, global planarization of the surface of a wafer is desired. Here, the substrate surface may be a semiconductor layer surface having a device formed thereon, the surface of an insulating layer formed on the aforementioned semiconductor layer, or the surface of an electrically-conductive layer formed on the aforementioned insulating film.
For example, a chemical mechanical polishing (CMP) apparatus, such as that described below, is known as an apparatus for performing micro-planarization, not to mention global planarization, on the aforementioned types of substrates.
Conventional Polishing Method (A): As shown in FIG. 7, the chemical mechanical polishing apparatus (disclosed in Japanese Unexamined Patent Publication No. 5-74749) comprises a table 101 with a polishing cross 102 being affixed to a processing surface of the table 101; and a top ring 110 having a resilient member 111, and within which, a pressurization fluid 112 is enclosed. In this chemical mechanical polishing apparatus, a wafer 103, placed on the polishing cross 102, which is affixed to the table 101, is pressed by the resilient member 111 of the top ring 110 with a uniform pressing (processing) force. While a polishing liquid (not shown) is being supplied, the table 101, which does not rotate, undergoes a circular motion in order to polish the surface of a device on the wafer 103.
Conventional Polishing Method (B): The polishing apparatus shown in FIGS. 8(A) and 8(B) comprises a top ring 210 and a turntable 201, each of which rotates, wherein a semiconductor wafer 203 is placed between the turntable 201 and the top ring 210. While a polishing liquid 221 is being supplied from a nozzle 220, a predetermined processing pressure is exerted onto the surface of the semiconductor wafer 203 to polish it. In this polishing apparatus, the semiconductor wafer 203 is fitted to the inner diameter portion of a guide ring 213 projecting at the outer peripheral portion of the top ring 210. The amount of downward projection of a plurality of concentrically disposed projecting portions 212a, 212b, and 212c is varied in stages such that the amount of projection of the center projecting portion 212a is greatest. With the center projecting portion 212a projecting downward, the semiconductor wafer 203 is pressed and polished.
In both of the above-described conventional methods (A) and (B), however, the substrate frequently gets dislodged from the top ring during polishing.
In addition, in the conventional method (A), it is difficult to fit the substrate to the top ring and to remove it from the top ring. Further, in the conventional method (B), the surface of the substrate to be polished does not match the polishing (processing) surface of the turntable, that is, the surface of the polishing tool. In this case, for example, the thickness of the insulating layer will vary with the location on the integrated circuit (IC) chip.